1. Field of the Invention
The present invention relates to a package structure and a package process thereof. More particularly, the present invention relates to the package structure and the package process suitable for stacked package of semiconductor device.
2. Description of Related Art
In today's information society, users all seek after electronic products with high speed, high quality and multiple functions. In terms of the product exterior appearance, electronic product designs reveal a trend of light weight, thinness and compactness. Stacked package of semiconductor devices are accordingly developed to meet the above requirements.
In the stacked semiconductor device package, several semiconductor devices are perpendicularly stacked together in the same package structure so that the package density is improved and the dimension of the package structure is decreased. Furthermore, by using three-dimensional stacking method to decrease the path length of the signal transmission between the semiconductor devices, rate of the signal transmission is improved and the semiconductor devices with different functions can be combined in the same package structure.
The conventional stacked semiconductor device package firstly stacks plural semiconductor devices together to form a stacked structure of semiconductor devices, wherein at least one of the semiconductor devices has a plurality of through silicon vias (TSVs) to electrically connect the semiconductor devices together through the TSVs. Then the stacked structure of semiconductor devices is bonded to a circuit board through the TSVs, and a molding compound is formed on the circuit board to preserve the stacked structure of semiconductor devices. In other words, the prior art forms the stacked structure of semiconductor devices first and then bonded the stacked structure on the circuit board.
However, in the conventional manufacturing method of stacked semiconductor device package, the kind or circuit layout of the semiconductor devices needs to be predetermined at the start of the package process, and thus the selectivity or the collocation of semiconductor device is restricted.